This invention relates generally to logarithmic amplifiers, and, more particularly, to a multi-stage logarithmic amplifier of the "progressive-compression" type including a multi-stage synchronous demodulator circuit.
Progressive-compression type logarithmic amplifiers are well known in the art and are widely employed to provide high-speed response to signals having a large dynamic range, often in applications where an automatic gain control circuit would be inapplicable due to its slow response to changes in signal amplitude. Progressive-compression type logarithmic amplifiers synthesize a logarithmic function through progressive compression of the input signal over many amplifier stages (typically five to ten). Each amplifier stage has a relatively low linear gain (typically two to four) up to some critical level. Above the critical level the incremental gain of the amplifier stage is reduced, and in some cases is zero. Progressive-compression type logarithmic amplifiers are not to be confused with single stage junction-based logarithmic amplifiers, which have severely limited frequency response. The discussion below is limited to progressive-compression type logarithmic amplifiers.
There are two types of logarithmic amplifiers: demodulating and baseband. A demodulating type of logarithmic amplifier 10 (sometimes referred to as a "successive-detection" logarithmic amplifier) is shown in FIG. 1. The input signal received at circuit node 12 is typically a sinusoidal RF signal and the output at circuit node 20 is a signal that is proportional to the logarithm (i.e., the decibel magnitude) of the input signal envelope, which is essentially a measure of the input signal power over an interval that is relatively long in comparison to the period of the input signal.
Demodulating logarithmic amplifier 10 includes a number of serially coupled linear amplifier/limiter stages 14 and a number of detector stages 16 coupled to the output of each amplifier 14, as well as a detector stage 16A coupled to the input of the first amplifier 14. Each detector 16 is typically a rectifier, which is actually realized as a transconductance element based upon the rectifying characteristic of one or more transistors represented by diode 17. The transconductance simplifies the summation o the outputs of each detector 16, since the output signals are in current form. The output current from each detector 16 is summed on current bus 24, converted from a current into a voltage at circuit node 25 by resistor 15 (or a transimpedance amplifier stage), and filtered by low-pass filter 18. It should be noted that detectors stages 16 can be implemented having a voltage output. In that case, a separate voltage summing circuit, rather than a simple current bus, is required to add the voltage outputs.
The DC transfer function of an amplifier/limiter stage 14 is shown in FIG. 1A. The gain of amplifier stage 14 remains linear with a constant gain of A for small signals. At signal input levels above a predetermined knee voltage E, the gain drops to zero. A corresponding label of "A/0" is therefore associated with each amplifier stage 14 shown in FIG. 1. Each amplifier stage 14 can amplify/limit bipolar input signals. The basic equations describing the transfer function are thus: ##EQU1##
In realizing the synthesized logarithmic output, it is important that the gain A and limiting performance at the knee voltage E of all stages be made as precisely equal as possible.
While a piecewise linear and limiting transfer function is shown in solid lines in FIG. 1A, the more commonly realized hyperbolic tangent transfer function is shown in dashed lines. An amplifier using a simple differential pair of bipolar transistors, for example, has a hyperbolic tangent transfer function, i.e. the differential output current (or voltage with a linear resistive load) divided by the differential input voltage.
The overall synthesized logarithmic output of amplifier 10 is shown in FIG. 1B for eight amplifier/limiter stages. Note that the logarithmic function, which is synthesized with linear amplifiers, is not ideal. An error or "ripple" is present, which is strictly a function of the gain of each amplifier stage. Each "cusp" or transition point in the synthesized function, however, lies directly along a logarithmic curve of the form: EQU V.sub.W =V.sub.Y log(V.sub.X /V.sub.Z) [4]
wherein V.sub.W is the output voltage, V.sub.X is the input voltage, V.sub.Y is the slope voltage, and V.sub.Z is the intercept voltage.
The second type of logarithmic amplifier is the baseband amplifier 20, shown in FIG. 2, which operates according to a similar progressive-compression technique for synthesizing a logarithmic function. The input signal received at circuit node 12 is typically a pulse or other baseband signal, and the output at circuit node 24 is a signal that is proportional to the logarithm of the instantaneous value of the input signal. Some baseband logarithmic amplifiers accept input signals of a single polarity since the ln(x) function contains a singularity at the origin. Other functions, however, which do not contain a singularity and quickly converge to the ln(x) function, such as the sinh.sup.-1 (x) function, can be equally easily synthesized using very similar circuit techniques and enable the amplifier to accept bipolar input signals.
Referring now to FIG. 2, baseband logarithmic amplifier 20 includes a number of serially coupled linear amplifier/limiter stages 14 and a number of transconductance stages 19 coupled to the output of each amplifier 14, as well as a transconductance stage 19A coupled to the input of the first amplifier 14. Each stage 19 is typically a linear transconductance element, which again simplifies the summation of the outputs of each stage 19 since the output signal is in current form. The output current from each stage 19 is summed on the current bus 24, and directly converted from a current into an output voltage by resistor 15 at circuit node 25. Again, a transimpedance amplifier can be used in place of resistor 15 to convert the total output current into a voltage.
Both prior logarithmic amplifiers 10 and 20 exhibit a noise problem if bandwidth-limiting filters are not included between each amplifier/limiter stage 14. This is because all noise signals, including self-generated noise signals, that appear at the input 12 or any of the intermediate nodes, are amplified and make a contribution to total output noise at node 25. In a logarithmic amplifier realized using discrete or hybrid technology, such filters can be included and the noise bandwidth minimized. However, these filters complicate the accurate synthesis of the logarithmic function and impose fixed frequency characteristics on the circuit. In integrated form the interstage filters are generally not possible due to the inherent limitations of semiconductor processing technology. Wideband noise, therefore, remains a major problem that can only be minimized through traditional approaches involving tradeoffs, in particular increased power consumption.
It is apparent that neither logarithmic amplifier 10 nor logarithmic amplifier 20 is tunable in integrated form. In the discrete and hybrid versions, the same interstage filters that minimize noise bandwidth can also be tuned to respond to only a predetermined range of input signal frequencies. These filters are not generally realizable in integrated circuits.
The present invention also incorporates a multi-stage synchronous demodulator circuit into the multi-stage progressive-compression logarithmic amplifier. Synchronous demodulator circuits, sometimes referred to as "coherent detectors", are well known in the art and are used to recover information from signals buried in noise. A signal can be recovered even if the signal-to-noise ratio is well below 0 dB. They are widely used in many professional and military applications including radar, sonar, medicine, radio astronomy, and consumer products.
Referring now to FIG. 3 a synchronous demodulator circuit 32 is simply a sign-alternating stage 31, which can be implemented with a multiplier configured as a balanced modulator, followed by a low pass filter 33. The sign-alternating stage 31 has a first input 34 for receiving an input signal, a second input 36 for receiving a clock signal, and an output coupled to the input of the low pass filter 33. The sign-alternating stage 31 has an associated gain, K, assuming a voltage output. The output 38 of the low pass filter 33 provides the demodulated output signal.
In operation, the output signal at node 38 is essentially full wave rectified if the input signal is at the same frequency and phase of the clock signal. In other words, the sign of the input signal is preserved during one clock state, and the sign of the input signal is inverted during the other clock state. If the corner frequency of the low pass filter 33 is well below the frequency of the input Signal, the output of the synchronous demodulator 32 is simply the mean value of the rectified input signal. Note that if the input signal is in quadrature with the clock signal (90.degree. out of phase) the output averages to zero. One important aspect of synchronous demodulators is that additive noise, even high levels of additive noise, traveling on the input signal is not full-wave rectified. It can be shown that the sign-alteration provided by stage 31 does not alter the mean value of the noise, which is zero. In fact, any signal not properly related to the input signal is rejected (averaged to zero). The effectiveness of the rejection of noise depends upon how much time is allowed for the averaging process. Synchronous demodulator circuits are not to be confused with simple absolute value and filter circuits, which do not average additive noise to zero.
What is desired is a novel circuit block that combines the best features of prior art progressive-compression type logarithmic amplifiers and synchronous demodulators to provide a tunable integrated logarithmic amplifier having improved noise performance without interstage filters.